Invention Grant
- Patent Title: Formation of an integrated circuit structure with reduced dishing in metallization levels
- Patent Title (中): 形成集成电路结构，减少金属化水平的凹陷
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Application No.: US11649015Application Date: 2007-01-03
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Publication No.: US07727894B2Publication Date: 2010-06-01
- Inventor: Sailesh Chittipeddi , Sailesh Merchant
- Applicant: Sailesh Chittipeddi , Sailesh Merchant
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/4763 ; H01L21/302 ; H01L21/461
Abstract:
An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.
Public/Granted literature
- US20070228572A1 Formation of an integrated circuit structure with reduced dishing in metallization levels Public/Granted day:2007-10-04
Information query
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