Invention Grant
US07728361B2 Method of testing an integrated circuit die, and an integrated circuit die
有权
集成电路管芯的测试方法和集成电路管芯
- Patent Title: Method of testing an integrated circuit die, and an integrated circuit die
- Patent Title (中): 集成电路管芯的测试方法和集成电路管芯
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Application No.: US12113881Application Date: 2008-05-01
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Publication No.: US07728361B2Publication Date: 2010-06-01
- Inventor: Kangping Zhang , Fong-Long Lin
- Applicant: Kangping Zhang , Fong-Long Lin
- Applicant Address: US CA Sunnyvale
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: DLA Piper LLP (US)
- Main IPC: H01L27/10
- IPC: H01L27/10 ; H01L21/82 ; H01L23/48
Abstract:
In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
Public/Granted literature
- US20090273007A1 Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die Public/Granted day:2009-11-05
Information query
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