Invention Grant
- Patent Title: Memory utilizing oxide nanolaminates
- Patent Title (中): 记忆利用氧化物Nanolaminates
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Application No.: US12205338Application Date: 2008-09-05
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Publication No.: US07728626B2Publication Date: 2010-06-01
- Inventor: Leonard Forbes , Kie Y. Ahn
- Applicant: Leonard Forbes , Kie Y. Ahn
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H03K19/177
- IPC: H03K19/177 ; H03K19/094 ; H01L25/00

Abstract:
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.
Public/Granted literature
- US20090002025A1 MEMORY UTILIZING OXIDE NANOLAMINATES Public/Granted day:2009-01-01
Information query
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