The invention relates to an apparatus comprising a pipelined converter, such as a pipelined ADC. The pipelined converter has a first set of stages and a second set of stages. A clocking circuit is configured to generate a plurality of clocking signals for the pipelined converter. The plurality of clocking signals comprise a first clocking signal at a first voltage level that is provided to the first set of stages and a second clocking signal at a second voltage level that is provided to the second set of stages.