A semiconductor integrated circuit having an ESD protection circuit enhancing a durability against thermal destruction is provided. The semiconductor integrated circuit configured by a plurality of MOSFETs each having an SOI structure formed on a silicon substrate includes a functional circuit having an external connection signal terminal, a pair of power terminals and at least one of the MOSFETs. The semiconductor integrated circuit also includes at least one ESD protection circuit having a first terminal and a second terminal connected to the signal terminal and the power terminals, respectively. The ESD protection circuit includes at least one first MOSFET of the MOSFETs formed on the silicon substrate. The first MOSFET has a drain connected to the first terminal, a gate connected to the second terminal, and a source connected to the second terminal. The at least one ESD protection circuit also includes at least one second MOSFET of the MOSFETs formed adjacent to the first MOSFET on the silicon substrate. The second MOSFET has a gate connected to the first terminal and the same conductivity type as the first MOSFET.