A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. The arrangement of the ROM is such that the word line of a selected row is pulled down to a ground voltage (Vgnd). Non-selected word lines are kept at a supply voltage VDD to ensure that unwanted rows will not have any sub-threshold current (as Vds=0). So during read “1” operation (that is when bit line (BL) is high) load cells would not leak unnecessarily. Thus the ROM achieves a high operational speed with reduced leakage and low power consumption.