Invention Grant
- Patent Title: Method and system for testing an integrated circuit
- Patent Title (中): 用于测试集成电路的方法和系统
-
Application No.: US12022422Application Date: 2008-01-30
-
Publication No.: US07729186B2Publication Date: 2010-06-01
- Inventor: Joerg Kliewer , Klaus Nierle , Martin Versen
- Applicant: Joerg Kliewer , Klaus Nierle , Martin Versen
- Applicant Address: DE Munich
- Assignee: Qimonda AG
- Current Assignee: Qimonda AG
- Current Assignee Address: DE Munich
- Agency: Coats & Bennett, P.L.L.C.
- Priority: DE102007004555 20070130
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.
Public/Granted literature
- US20080205173A1 Method and System for Testing an Integrated Circuit Public/Granted day:2008-08-28
Information query