Invention Grant
- Patent Title: Adaptively reducing memory latency in a system
- Patent Title (中): 适应性地减少系统中的内存延迟
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Application No.: US11526431Application Date: 2006-09-25
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Publication No.: US07730264B1Publication Date: 2010-06-01
- Inventor: Krishnakanth Sistla
- Applicant: Krishnakanth Sistla
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
In one embodiment, the present invention includes a method for routing an early request for requested data on a bypass path around a transaction processing path of a first agent if the requested data is not present in a cache memory of the first agent, and opportunistically transmitting the early request from the first agent to a second agent based on load conditions of an interconnect between the first agent and the second agent. In this way, reduced memory latencies may be realized. Other embodiments are described and claimed.
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