Invention Grant
US07730283B2 Simple load and store disambiguation and scheduling at predecode
失效
简单的加载和存储消除歧义和调度在预编码
- Patent Title: Simple load and store disambiguation and scheduling at predecode
- Patent Title (中): 简单的加载和存储消除歧义和调度在预编码
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Application No.: US12174529Application Date: 2008-07-16
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Publication No.: US07730283B2Publication Date: 2010-06-01
- Inventor: David A. Luick
- Applicant: David A. Luick
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson & Sheridan LLP
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
Embodiments of the invention provide a processor for executing instructions. In one embodiment, the processor includes circuitry to receive a load instruction and a store instruction to be executed in the processor and detect a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The processor further includes circuitry to schedule execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict.
Public/Granted literature
- US20080276074A1 SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE Public/Granted day:2008-11-06
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