Invention Grant
US07730283B2 Simple load and store disambiguation and scheduling at predecode 失效
简单的加载和存储消除歧义和调度在预编码

Simple load and store disambiguation and scheduling at predecode
Abstract:
Embodiments of the invention provide a processor for executing instructions. In one embodiment, the processor includes circuitry to receive a load instruction and a store instruction to be executed in the processor and detect a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The processor further includes circuitry to schedule execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict.
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