Invention Grant
US07730284B2 Pipelined instruction processor with data bypassing and disabling circuit
有权
带数据旁路和禁用电路的流水线指令处理器
- Patent Title: Pipelined instruction processor with data bypassing and disabling circuit
- Patent Title (中): 带数据旁路和禁用电路的流水线指令处理器
-
Application No.: US10549368Application Date: 2004-03-17
-
Publication No.: US07730284B2Publication Date: 2010-06-01
- Inventor: Balakrishnan Srinivasan , Ramanathan Sethuraman , Carlos Antonio Alba Pinto
- Applicant: Balakrishnan Srinivasan , Ramanathan Sethuraman , Carlos Antonio Alba Pinto
- Applicant Address: NL Eindhoven
- Assignee: Koninklijke Philips Electronics N.V.
- Current Assignee: Koninklijke Philips Electronics N.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP031007107 20030319
- International Application: PCT/IB2004/050270 WO 20040317
- International Announcement: WO2004/084065 WO 20040930
- Main IPC: G06F9/30
- IPC: G06F9/30
Abstract:
An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.
Public/Granted literature
- US20060212686A1 Pipelined instruction processor with data bypassing Public/Granted day:2006-09-21
Information query
