Invention Grant
US07730337B2 Method and apparatus for asserting a hardware pin to disable a data bus connecting a processor and a chipset during power saving state
有权
用于在省电状态期间断言硬件引脚以禁用连接处理器和芯片组的数据总线的方法和装置
- Patent Title: Method and apparatus for asserting a hardware pin to disable a data bus connecting a processor and a chipset during power saving state
- Patent Title (中): 用于在省电状态期间断言硬件引脚以禁用连接处理器和芯片组的数据总线的方法和装置
-
Application No.: US11626622Application Date: 2007-01-24
-
Publication No.: US07730337B2Publication Date: 2010-06-01
- Inventor: Jen-Chieh Chen
- Applicant: Jen-Chieh Chen
- Applicant Address: TW Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW Taipei
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/00

Abstract:
A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.
Public/Granted literature
- US20080178026A1 COMPUTER SYSTEM AND POWER SAVING METHOD THEREOF Public/Granted day:2008-07-24
Information query