A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.