Invention Grant
US07730376B2 Providing high availability in a PCI-Express™ link in the presence of lane faults
有权
在存在通道故障的情况下,在PCI-Express™链路中提供高可用性
- Patent Title: Providing high availability in a PCI-Express™ link in the presence of lane faults
- Patent Title (中): 在存在通道故障的情况下,在PCI-Express™链路中提供高可用性
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Application No.: US12056777Application Date: 2008-03-27
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Publication No.: US07730376B2Publication Date: 2010-06-01
- Inventor: Debendra Das Sharma
- Applicant: Debendra Das Sharma
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Derek J. Reynolds
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00

Abstract:
A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.
Public/Granted literature
- US20080178052A1 PROVIDING HIGH AVAILABILITY IN A PCI-EXPRESSTM LINK IN THE PRESENCE OF LANE FAULTS Public/Granted day:2008-07-24
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