Invention Grant
- Patent Title: Method of full semiconductor chip timing closure
- Patent Title (中): 全半导体芯片时序闭合的方法
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Application No.: US11256807Application Date: 2005-10-24
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Publication No.: US07730437B1Publication Date: 2010-06-01
- Inventor: Purushothaman Ramakrishnan , Pattikad Narayanan Ravindran , Chirakkal Varriam Unnikrishnan , Rakesh Mehrotra
- Applicant: Purushothaman Ramakrishnan , Pattikad Narayanan Ravindran , Chirakkal Varriam Unnikrishnan , Rakesh Mehrotra
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.
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