Invention Grant
US07730443B2 System and method for checking a length of a wire path between a capacitor and a via of a PCB design
失效
用于检查PCB设计的电容器和通孔之间的线路的长度的系统和方法
- Patent Title: System and method for checking a length of a wire path between a capacitor and a via of a PCB design
- Patent Title (中): 用于检查PCB设计的电容器和通孔之间的线路的长度的系统和方法
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Application No.: US11951284Application Date: 2007-12-05
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Publication No.: US07730443B2Publication Date: 2010-06-01
- Inventor: Shou-Kuo Hsu , Chun-Shan Hsiao
- Applicant: Shou-Kuo Hsu , Chun-Shan Hsiao
- Applicant Address: TW Tu-Cheng, Taipei Hsien
- Assignee: Hon Hai Precision Industry Co., Ltd.
- Current Assignee: Hon Hai Precision Industry Co., Ltd.
- Current Assignee Address: TW Tu-Cheng, Taipei Hsien
- Agent Frank R. Niranjan
- Priority: CN200710200152 20070202
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45

Abstract:
A method for checking a length of a wire path between a capacitor and a via of the PCB design obtains length criteria and information on capacitors from a database, selects one or more capacitors and pins of the selected capacitors from the obtained information on capacitors and selects one of the length criteria, and obtains positions of selected capacitors and positions of vias corresponding to the positions of selected capacitors from the database. The method further calculates each length of a wire path between a selected capacitor and a corresponding via according to the position of the capacitor and the position of the via, determines whether each calculated length of a wire path between a selected capacitor and a corresponding via is acceptable according to a comparison with the selected length criterion, and outputs check results of the determining step.
Public/Granted literature
- US20080189669A1 SYSTEM AND METHOD FOR CHECKING A LENGTH OF A WIRE PATH BETWEEN A CAPACITOR AND A VIA OF A PCB DESIGN Public/Granted day:2008-08-07
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