Invention Grant
- Patent Title: Method of forming a MOS device with an additional layer
- Patent Title (中): 用附加层形成MOS器件的方法
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Application No.: US11174683Application Date: 2005-07-05
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Publication No.: US07732289B2Publication Date: 2010-06-08
- Inventor: Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
- Applicant: Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/366
- IPC: H01L21/366

Abstract:
A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
Public/Granted literature
- US20070010051A1 Method of forming a MOS device with an additional layer Public/Granted day:2007-01-11
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