Invention Grant
- Patent Title: Post last wiring level inductor using patterned plate process
- Patent Title (中): 使用图案板工艺后最后布线级电感器
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Application No.: US12170473Application Date: 2008-07-10
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Publication No.: US07732295B2Publication Date: 2010-06-08
- Inventor: Anil Kumar Chinthakindi , Douglas Duane Coolbaugh , John Edward Florkey , Jeffrey Peter Gambino , Zhong-Xiang He , Anthony Kendall Stamper , Kunal Vaed
- Applicant: Anil Kumar Chinthakindi , Douglas Duane Coolbaugh , John Edward Florkey , Jeffrey Peter Gambino , Zhong-Xiang He , Anthony Kendall Stamper , Kunal Vaed
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Anthony J. Canale
- Main IPC: H01L21/20
- IPC: H01L21/20
Abstract:
A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.
Public/Granted literature
- US20080293210A1 POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS Public/Granted day:2008-11-27
Information query
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