Invention Grant
- Patent Title: Gate metal routing for transistor with checkerboarded layout
- Patent Title (中): 晶体管的栅极金属布线,具有棋盘布局
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Application No.: US12291569Application Date: 2008-11-12
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Publication No.: US07732860B2Publication Date: 2010-06-08
- Inventor: Vijay Parthasarathy
- Applicant: Vijay Parthasarathy
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Bradley J. Bereznak
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
Public/Granted literature
- US20090072302A1 Gate metal routing for transistor with checkerboarded layout Public/Granted day:2009-03-19
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