Invention Grant
- Patent Title: Semiconductor device fabrication method and semiconductor device fabricated thereby
- Patent Title (中): 由此制造半导体器件制造方法和半导体器件
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Application No.: US11956072Application Date: 2007-12-13
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Publication No.: US07732875B2Publication Date: 2010-06-08
- Inventor: Masakatsu Tsuchiaki
- Applicant: Masakatsu Tsuchiaki
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2007-049092 20070228
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 μm in length and running along a Si direction.
Public/Granted literature
- US20080203440A1 SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE FABRICATED THEREBY Public/Granted day:2008-08-28
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