Invention Grant
US07732924B2 Semiconductor wiring structures including dielectric cap within metal cap layer
有权
包括金属盖层内的电介质盖的半导体布线结构
- Patent Title: Semiconductor wiring structures including dielectric cap within metal cap layer
- Patent Title (中): 包括金属盖层内的电介质盖的半导体布线结构
-
Application No.: US11761495Application Date: 2007-06-12
-
Publication No.: US07732924B2Publication Date: 2010-06-08
- Inventor: Kaushik Chanda , Ronald G. Filippi , Ping-Chuan Wang , Chih-Chao Yang
- Applicant: Kaushik Chanda , Ronald G. Filippi , Ping-Chuan Wang , Chih-Chao Yang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Ian D. MacKinnon
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.
Public/Granted literature
- US20080308942A1 SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER Public/Granted day:2008-12-18
Information query
IPC分类: