Invention Grant
- Patent Title: Semiconductor testing circuit and semiconductor testing method
- Patent Title (中): 半导体测试电路和半导体测试方法
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Application No.: US12173860Application Date: 2008-07-16
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Publication No.: US07733112B2Publication Date: 2010-06-08
- Inventor: Satoshi Kishimoto , Tomohiko Kanemitsu
- Applicant: Satoshi Kishimoto , Tomohiko Kanemitsu
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Steptoe & Johnson LLP
- Priority: JP2007-186384 20070718
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/26 ; G01R31/28

Abstract:
A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.
Public/Granted literature
- US20090021279A1 SEMICONDUCTOR TESTING CIRCUIT AND SEMICONDUCTOR TESTING METHOD Public/Granted day:2009-01-22
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