Invention Grant
- Patent Title: Nonvolatile latch circuit and nonvolatile flip-flop circuit
- Patent Title (中): 非易失性锁存电路和非易失性触发器电路
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Application No.: US11848864Application Date: 2007-08-31
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Publication No.: US07733145B2Publication Date: 2010-06-08
- Inventor: Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
- Applicant: Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-264590 20060928
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K3/45

Abstract:
A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate functioning as an inverter or a gate outputting the constant voltage in response to the first control signal; a second gate part controlling to load or intercept the output of the second logic gate based on an inverted signal of the gate signal and sends the output of the second logic gate to an first input terminal of the first logic gate; and first and second injection type MTJ elements provided between the driving power supply and the first and second logic gates and changing in resistance depending upon a current flow direction.
Public/Granted literature
- US20080080231A1 NONVOLATILE LATCH CIRCUIT AND NONVOLATILE FLIP-FLOP CIRCUIT Public/Granted day:2008-04-03
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