Invention Grant
US07733147B2 Delay circuit of delay locked loop having single and dual delay lines and control method of the same
有权
具有单延迟线和双延迟线的延迟锁定环路的延迟电路及其控制方法
- Patent Title: Delay circuit of delay locked loop having single and dual delay lines and control method of the same
- Patent Title (中): 具有单延迟线和双延迟线的延迟锁定环路的延迟电路及其控制方法
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Application No.: US12172887Application Date: 2008-07-14
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Publication No.: US07733147B2Publication Date: 2010-06-08
- Inventor: Hyun-Woo Lee , Won-Joo Yun
- Applicant: Hyun-Woo Lee , Won-Joo Yun
- Applicant Address: KR
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR
- Agency: Baker & McKenzie LLP
- Priority: KR10-2007-0128301 20071211
- Main IPC: H03H11/26
- IPC: H03H11/26
Abstract:
A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.
Public/Granted literature
- US20090146709A1 DELAY CIRCUIT OF DELAY LOCKED LOOP HAVING SINGLE AND DUAL DELAY LINES AND CONTROL METHOD OF THE SAME Public/Granted day:2009-06-11
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