Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier, the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor.