Invention Grant
US07733150B2 Method and apparatus for adaptive clock phase control for LSI power reduction
有权
用于LSI功率降低的自适应时钟相位控制的方法和装置
- Patent Title: Method and apparatus for adaptive clock phase control for LSI power reduction
- Patent Title (中): 用于LSI功率降低的自适应时钟相位控制的方法和装置
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Application No.: US12192385Application Date: 2008-08-15
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Publication No.: US07733150B2Publication Date: 2010-06-08
- Inventor: Chiaki Takano
- Applicant: Chiaki Takano
- Applicant Address: JP Tokyo
- Assignee: Sony Computer Entertainment Inc.
- Current Assignee: Sony Computer Entertainment Inc.
- Current Assignee Address: JP Tokyo
- Agency: Gibson & Dernier LLP
- Agent Matthew B. Dernier, Esq.
- Main IPC: G06F1/04
- IPC: G06F1/04

Abstract:
Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
Public/Granted literature
- US20100039152A1 METHOD AND APPARATUS FOR ADAPTIVE CLOCK PHASE CONTROL FOR LSI POWER REDUCTION Public/Granted day:2010-02-18
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