Invention Grant
- Patent Title: Noise-reducing transistor arrangement
- Patent Title (中): 降噪晶体管布置
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Application No.: US10583538Application Date: 2004-12-03
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Publication No.: US07733157B2Publication Date: 2010-06-08
- Inventor: Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
- Applicant: Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Dickstein, Shapiro, LLP.
- Priority: DE10358713 20031215
- International Application: PCT/DE2004/002657 WO 20041203
- International Announcement: WO2005/060099 WO 20050630
- Main IPC: H03K17/687
- IPC: H03K17/687

Abstract:
Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
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