Invention Grant
US07733724B2 Controlling global bit line pre-charge time for high speed eDRAM
有权
控制高速eDRAM的全局位线预充电时间
- Patent Title: Controlling global bit line pre-charge time for high speed eDRAM
- Patent Title (中): 控制高速eDRAM的全局位线预充电时间
-
Application No.: US11970188Application Date: 2008-01-07
-
Publication No.: US07733724B2Publication Date: 2010-06-08
- Inventor: Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
- Applicant: Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
Public/Granted literature
- US20090141570A1 Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM Public/Granted day:2009-06-04
Information query