Invention Grant
US07734041B2 System and method for de-scrambling and bit-order-reversing payload bytes in an Asynchronous Transfer Mode cell 失效
用于在异步传输模式单元中解扰和位顺序反转有效载荷字节的系统和方法

System and method for de-scrambling and bit-order-reversing payload bytes in an Asynchronous Transfer Mode cell
Abstract:
A method and apparatus are disclosed for efficiently de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards on a processor. In a preferred embodiment, this is achieved by providing an instruction for de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble and bit-order-reverse data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.
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