Invention Grant
US07735041B2 Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices 失效
实现修改的路由网格以增加可定制的逻辑阵列设备的路由密度的方法和计算机可读介质

  • Patent Title: Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices
  • Patent Title (中): 实现修改的路由网格以增加可定制的逻辑阵列设备的路由密度的方法和计算机可读介质
  • Application No.: US11499913
    Application Date: 2006-08-03
  • Publication No.: US07735041B2
    Publication Date: 2010-06-08
  • Inventor: Lior AmarilioYoav Segal
  • Applicant: Lior AmarilioYoav Segal
  • Applicant Address: US CA Santa Clara
  • Assignee: ChipX, Inc.
  • Current Assignee: ChipX, Inc.
  • Current Assignee Address: US CA Santa Clara
  • Agency: Pillsbury Winthrop Shaw Pittman LLP
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices
Abstract:
Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association with the noncompliant connectivity grid in either a first direction or a second direction, which can be substantially orthogonal to the first direction in some embodiments. The via caps are configured to provide each via with an amount of overlap area for sufficient coverage. In some instances, the method also includes forming a configuration layer for routing among a subset of the vias to provide at least the amount of overlap area for each via in the subset, and for forming the via caps for unrouted vias that are not part of the subset.
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