Invention Grant
US07735053B2 Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method
失效
设计数据或掩模数据的校正方法和校正系统，设计数据或掩模数据的验证方法和验证系统，半导体集成电路的产量估算方法，改进设计规则的方法，掩模生产方法和半导体集成电路生产方法
- Patent Title: Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method
- Patent Title (中): 设计数据或掩模数据的校正方法和校正系统，设计数据或掩模数据的验证方法和验证系统，半导体集成电路的产量估算方法，改进设计规则的方法，掩模生产方法和半导体集成电路生产方法
-
Application No.: US11819397Application Date: 2007-06-27
-
Publication No.: US07735053B2Publication Date: 2010-06-08
- Inventor: Katsuhiko Harazaki
- Applicant: Katsuhiko Harazaki
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Nixon & Vanderhye P.C.
- Priority: JP2006-179489 20060629; JP2007-161906 20070619
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A validation/correction method is provided for design data or mask data by which a pattern which becomes critical in a process is extracted in advance so that the pattern can be corrected. Consequently, the process spec is achieved in a short period of time after OPC or process proximity effect correction (PPC).
Public/Granted literature
Information query
