Invention Grant
US07737040B2 Method of reducing critical dimension bias during fabrication of a semiconductor device
有权
在半导体器件制造期间减小临界尺寸偏压的方法
- Patent Title: Method of reducing critical dimension bias during fabrication of a semiconductor device
- Patent Title (中): 在半导体器件制造期间减小临界尺寸偏压的方法
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Application No.: US11983450Application Date: 2007-11-09
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Publication No.: US07737040B2Publication Date: 2010-06-15
- Inventor: Christopher Dennis Bencher , Melvin Warren Montgomery , Alexander Buxbaum , Yung-Hee Yvette Lee , Jian Ding , Gilad Almogy , Wendy H. Yeh
- Applicant: Christopher Dennis Bencher , Melvin Warren Montgomery , Alexander Buxbaum , Yung-Hee Yvette Lee , Jian Ding , Gilad Almogy , Wendy H. Yeh
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agent Shirley L. Church, Esq.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/311
Abstract:
An anti-reflective hard mask layer left on a radiation-blocking layer during fabrication of a reticle provides functionality when the reticle is used in a semiconductor device manufacturing process.
Public/Granted literature
- US20080096138A1 Method of reducing critical dimension bias during fabrication of a semiconductor device Public/Granted day:2008-04-24
Information query
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