Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US11242955Application Date: 2005-10-05
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Publication No.: US07737553B2Publication Date: 2010-06-15
- Inventor: Osamu Shibata , Yoshiyuki Saito
- Applicant: Osamu Shibata , Yoshiyuki Saito
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2004-293515 20041006
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
Fine-pitch first and second bonding pads are formed on a chip along its perimeter. The first bonding pads are formed at the peripheral parts on the chip, while the second bonding pads are formed inside the peripheral parts. An ESD protection circuit is connected to the first bonding pad, and an I/O circuit is connected to the second bonding pad. First and second bonding wires connect the first and second bonding pads to the same package pin, respectively. The second bonding wire is configured to be sufficiently longer than the first bonding wire, regardless of the pitch of the first bonding pads.
Public/Granted literature
- US20060071320A1 Semiconductor device Public/Granted day:2006-04-06
Information query
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