Invention Grant
- Patent Title: Method and tester for verifying the electrical connection integrity of a component to a substrate
- Patent Title (中): 用于验证部件到基板的电连接完整性的方法和测试器
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Application No.: US11862189Application Date: 2007-09-26
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Publication No.: US07737701B2Publication Date: 2010-06-15
- Inventor: Eddie L Williamson , Tak Yee Kwan
- Applicant: Eddie L Williamson , Tak Yee Kwan
- Applicant Address: US CA Santa Clara
- Assignee: Agilent Technologies, Inc.
- Current Assignee: Agilent Technologies, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G01R31/04
- IPC: G01R31/04 ; G01R31/08

Abstract:
A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate is disclosed. The method includes generating a step signal on one of the at least one signal path connected to a respective contact, and capturing a capacitively coupled signal due to the step signal at the contact. The method further includes determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. A tester in which the method is implemented is also disclosed.
Public/Granted literature
- US20090079440A1 METHOD AND TESTER FOR VERIFYING THE ELECTRICAL CONNECTION INTEGRITY OF A COMPONENT TO A SUBSTRATE Public/Granted day:2009-03-26
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