Invention Grant
US07738549B2 Architecture for very high-speed decision feedback sequence estimation 有权
非常高速的决策反馈序列估计架构

Architecture for very high-speed decision feedback sequence estimation
Abstract:
A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.
Information query
Patent Agency Ranking
0/0