Invention Grant
- Patent Title: Architecture for very high-speed decision feedback sequence estimation
- Patent Title (中): 非常高速的决策反馈序列估计架构
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Application No.: US11674530Application Date: 2007-02-13
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Publication No.: US07738549B2Publication Date: 2010-06-15
- Inventor: Arthur Abnous , Avanindra Madisetti , Christian A. J. Lutkemeyer
- Applicant: Arthur Abnous , Avanindra Madisetti , Christian A. J. Lutkemeyer
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Agency: McAndrews, Held & Malloy, Ltd.
- Main IPC: H03H7/30
- IPC: H03H7/30 ; H03H7/40 ; H03K5/159

Abstract:
A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.
Public/Granted literature
- US20070189376A1 ARCHITECTURE FOR VERY HIGH-SPEED DECISION FEEDBACK SEQUENCE ESTIMATION Public/Granted day:2007-08-16
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