Invention Grant
- Patent Title: Method of disposing dummy pattern
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Application No.: US11306392Application Date: 2005-12-27
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Publication No.: US07743356B2Publication Date: 2010-06-22
- Inventor: Koji Yomogita
- Applicant: Koji Yomogita
- Applicant Address: JP Tokyo
- Assignee: Oki Semiconductor Co., Ltd.
- Current Assignee: Oki Semiconductor Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Rabin & Berdo, P.C.
- Priority: JP2005-009626 20050117
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base.
Public/Granted literature
- US20060199284A1 METHOD OF DISPOSING DUMMY PATTERN Public/Granted day:2006-09-07
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