Invention Grant
US07746251B2 High speed serializer/deserializer transmit architecture 有权
高速串行器/解串器传输架构

  • Patent Title: High speed serializer/deserializer transmit architecture
  • Patent Title (中): 高速串行器/解串器传输架构
  • Application No.: US11939523
    Application Date: 2007-11-13
  • Publication No.: US07746251B2
    Publication Date: 2010-06-29
  • Inventor: Jason Gonzalez
  • Applicant: Jason Gonzalez
  • Applicant Address: US CA San Diego
  • Assignee: Qualcomm Incorporated
  • Current Assignee: Qualcomm Incorporated
  • Current Assignee Address: US CA San Diego
  • Agent François A. Pelaez
  • Main IPC: H03M9/00
  • IPC: H03M9/00
High speed serializer/deserializer transmit architecture
Abstract:
A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.
Public/Granted literature
Information query
Patent Agency Ranking
0/0