Invention Grant
US07746606B2 ESD protection for integrated circuits having ultra thin gate oxides
有权
具有超薄栅极氧化物的集成电路的ESD保护
- Patent Title: ESD protection for integrated circuits having ultra thin gate oxides
- Patent Title (中): 具有超薄栅极氧化物的集成电路的ESD保护
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Application No.: US10990641Application Date: 2004-11-16
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Publication No.: US07746606B2Publication Date: 2010-06-29
- Inventor: Eugene R. Worley
- Applicant: Eugene R. Worley
- Applicant Address: US CA Newport Beach
- Assignee: Conexant Systems, Inc.
- Current Assignee: Conexant Systems, Inc.
- Current Assignee Address: US CA Newport Beach
- Agency: Farjami & Farjami LLP
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H3/20

Abstract:
According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.
Public/Granted literature
- US20050152081A1 ESD protection for integrated circuits having ultra thin gate oxides Public/Granted day:2005-07-14
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