Invention Grant
US07746608B2 Methodology to guard ESD protection circuits against precharge effects
有权
保护ESD保护电路免受预充电影响的方法
- Patent Title: Methodology to guard ESD protection circuits against precharge effects
- Patent Title (中): 保护ESD保护电路免受预充电影响的方法
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Application No.: US11548019Application Date: 2006-10-10
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Publication No.: US07746608B2Publication Date: 2010-06-29
- Inventor: Chih-Ming Hung , Charvaka Duvvury
- Applicant: Chih-Ming Hung , Charvaka Duvvury
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H02H9/00
- IPC: H02H9/00
Abstract:
An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
Public/Granted literature
- US20070103826A1 METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS Public/Granted day:2007-05-10
Information query
