Invention Grant
US07746715B2 Erase and read schemes for charge trapping non-volatile memories
有权
擦除和读取电荷捕获非易失性存储器的方案
- Patent Title: Erase and read schemes for charge trapping non-volatile memories
- Patent Title (中): 擦除和读取电荷捕获非易失性存储器的方案
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Application No.: US10567070Application Date: 2004-08-04
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Publication No.: US07746715B2Publication Date: 2010-06-29
- Inventor: Michiel Jos Van Duuren
- Applicant: Michiel Jos Van Duuren
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP03102529 20030813
- International Application: PCT/IB2004/051382 WO 20040804
- International Announcement: WO2005/017911 WO 20050224
- Main IPC: G11C7/02
- IPC: G11C7/02

Abstract:
The present invention describes a method for operating an array of nonvolatile charge trapping memory devices. The method comprises before a block erase step (52) of substantially all of the non-volatile memory devices of the array, block programming (51) of substantially all of the non-volatile memory devices of the array. It is an advantage of the present invention that, by doing this, a further charge trapping nonvolatile memory device may be used as a reference cell, which is programmed and erased with the block-programming and block-erasing of the memory cells in the array, so that the reference cell shows the same cycling history as the memory cells in the array. This feature can be used for adapting read parameters to ageing of the memory cells. Corresponding devices are also provided.
Public/Granted literature
- US20060250855A1 Erase and read schemes for charge trapping non-volatile memories Public/Granted day:2006-11-09
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