Invention Grant
US07749829B2 Step height reduction between SOI and EPI for DSO and BOS integration
失效
SOI和EPI之间的步距降低DSO和BOS集成
- Patent Title: Step height reduction between SOI and EPI for DSO and BOS integration
- Patent Title (中): SOI和EPI之间的步距降低DSO和BOS集成
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Application No.: US11742755Application Date: 2007-05-01
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Publication No.: US07749829B2Publication Date: 2010-07-06
- Inventor: Gauri V. Karve , Debby Eades , Gregory S. Spencer , Ted R. White
- Applicant: Gauri V. Karve , Debby Eades , Gregory S. Spencer , Ted R. White
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Hamilton & Terrile, LLP
- Agent Michael Rocco Cannatti
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.
Public/Granted literature
- US20080274594A1 Step height reduction between SOI and EPI for DSO and BOS integration Public/Granted day:2008-11-06
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