Invention Grant
- Patent Title: Semiconductor device including a floating gate electrode having stacked structure
- Patent Title (中): 包括具有层叠结构的浮栅的半导体装置
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Application No.: US12050802Application Date: 2008-03-18
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Publication No.: US07749839B2Publication Date: 2010-07-06
- Inventor: Kazuo Hatakeyama
- Applicant: Kazuo Hatakeyama
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2005-180731 20050621
- Main IPC: H01L21/8247
- IPC: H01L21/8247

Abstract:
A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.
Public/Granted literature
- US20080171429A1 SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE ELECTRODE HAVING STACKED STRUCTURE Public/Granted day:2008-07-17
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