Invention Grant
- Patent Title: Gate patterning scheme with self aligned independent gate etch
- Patent Title (中): 具有自对准独立栅极蚀刻的栅极图案化方案
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Application No.: US12027444Application Date: 2008-02-07
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Publication No.: US07749903B2Publication Date: 2010-07-06
- Inventor: Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
- Applicant: Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Yuanmin Cai; Howard Cohn
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.
Public/Granted literature
- US20090203200A1 GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH Public/Granted day:2009-08-13
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