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US07749903B2 Gate patterning scheme with self aligned independent gate etch 失效
具有自对准独立栅极蚀刻的栅极图案化方案

Gate patterning scheme with self aligned independent gate etch
Abstract:
A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.
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