Invention Grant
- Patent Title: Dual-SiGe epitaxy for MOS devices
- Patent Title (中): 用于MOS器件的双SiGe外延
-
Application No.: US11633855Application Date: 2006-12-05
-
Publication No.: US07750338B2Publication Date: 2010-07-06
- Inventor: Yin-Pin Wang
- Applicant: Yin-Pin Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L31/00
- IPC: H01L31/00

Abstract:
A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.
Public/Granted literature
- US20080128746A1 Dual-SiGe epitaxy for MOS devices Public/Granted day:2008-06-05
Information query
IPC分类: