Invention Grant
- Patent Title: Semiconductor member, manufacturing method thereof, and semiconductor device
- Patent Title (中): 半导体元件及其制造方法以及半导体器件
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Application No.: US11711711Application Date: 2007-02-28
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Publication No.: US07750367B2Publication Date: 2010-07-06
- Inventor: Kazuya Notsu , Kiyofumi Sakaguchi , Nobuhiko Sato , Hajime Ikeda , Shoji Nishida
- Applicant: Kazuya Notsu , Kiyofumi Sakaguchi , Nobuhiko Sato , Hajime Ikeda , Shoji Nishida
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2004-265559 20040913
- Main IPC: H01L29/165
- IPC: H01L29/165 ; H01L29/786

Abstract:
An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
Public/Granted literature
- US20070272944A1 Semiconductor member, manufacturing method thereof, and semiconductor device Public/Granted day:2007-11-29
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