Invention Grant
- Patent Title: Self-aligned complementary LDMOS
- Patent Title (中): 自对准互补LDMOS
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Application No.: US12481108Application Date: 2009-06-09
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Publication No.: US07750401B2Publication Date: 2010-07-06
- Inventor: Jun Cai
- Applicant: Jun Cai
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Hiscock & Barclay, LLP
- Agent Thomas R. FitzGerald, Esq.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119

Abstract:
The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.
Public/Granted literature
- US20090242982A1 SELF-ALIGNED COMPLEMENTARY LDMOS Public/Granted day:2009-10-01
Information query
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