Invention Grant
- Patent Title: Semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件
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Application No.: US11823273Application Date: 2007-06-26
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Publication No.: US07750411B2Publication Date: 2010-07-06
- Inventor: Hirofumi Harada , Hisashi Hasegawa , Hideo Yoshino
- Applicant: Hirofumi Harada , Hisashi Hasegawa , Hideo Yoshino
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2006-176107 20060627
- Main IPC: H01L29/94
- IPC: H01L29/94

Abstract:
Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.
Public/Granted literature
- US20080006879A1 Semiconductor integrated circuit device Public/Granted day:2008-01-10
Information query
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