Invention Grant
- Patent Title: Method for bonding wafers to produce stacked integrated circuits
- Patent Title (中): 用于接合晶片以产生堆叠集成电路的方法
-
Application No.: US11484544Application Date: 2006-07-10
-
Publication No.: US07750488B2Publication Date: 2010-07-06
- Inventor: Robert Patti , Sangki Hong , Ramasamy Chockalingam
- Applicant: Robert Patti , Sangki Hong , Ramasamy Chockalingam
- Applicant Address: US IL Naperville
- Assignee: Tezzaron Semiconductor, Inc.
- Current Assignee: Tezzaron Semiconductor, Inc.
- Current Assignee Address: US IL Naperville
- Agent Calvin B. Ward
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.
Public/Granted literature
- US20080006938A1 Method for bonding wafers to produce stacked integrated circuits Public/Granted day:2008-01-10
Information query
IPC分类: