Invention Grant
- Patent Title: Semiconductor integrated circuit device having power reduction mechanism
- Patent Title (中): 具有降压机构的半导体集成电路装置
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Application No.: US11979100Application Date: 2007-10-31
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Publication No.: US07750668B2Publication Date: 2010-07-06
- Inventor: Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
- Applicant: Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, P.C.
- Priority: JP4-094070 19920414; JP4-094077 19920414; JP4-345901 19921225; JP5-022392 19930210
- Main IPC: H03K19/003
- IPC: H03K19/003 ; G05F1/10 ; G06F1/32

Abstract:
A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
Public/Granted literature
- US20080072085A1 Semiconductor integrated circuit device having power reduction mechanism Public/Granted day:2008-03-20
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