Invention Grant
- Patent Title: CMOS back-gated keeper technique
- Patent Title (中): CMOS后门控技术
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Application No.: US12538652Application Date: 2009-08-10
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Publication No.: US07750677B2Publication Date: 2010-07-06
- Inventor: Kerry Bernstein , Andres Bryant , Wilfried Haensch
- Applicant: Kerry Bernstein , Andres Bryant , Wilfried Haensch
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Vazken Alexanian
- Main IPC: H03K19/21
- IPC: H03K19/21

Abstract:
A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
Public/Granted literature
- US20090295432A1 CMOS BACK-GATED KEEPER TECHNIQUE Public/Granted day:2009-12-03
Information query
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