Invention Grant
US07750680B2 Automatic extension of clock gating technique to fine-grained power gating
有权
自动延长时钟门控技术到细粒度电源门控
- Patent Title: Automatic extension of clock gating technique to fine-grained power gating
- Patent Title (中): 自动延长时钟门控技术到细粒度电源门控
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Application No.: US11952937Application Date: 2007-12-07
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Publication No.: US07750680B2Publication Date: 2010-07-06
- Inventor: Mahesh Mamidipaka
- Applicant: Mahesh Mamidipaka
- Applicant Address: US CA San Jose
- Assignee: Apache Design Solutions, Inc.
- Current Assignee: Apache Design Solutions, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.
Public/Granted literature
- US20080088344A1 AUTOMATIC EXTENSION OF CLOCK GATING TECHNIQUE TO FINE-GRAINED POWER GATING Public/Granted day:2008-04-17
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